PSRAM64.h
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1 /****
2  * Sming Framework Project - Open Source framework for high efficiency native ESP8266 development.
3  * Created 2015 by Skurydin Alexey
4  * http://github.com/anakod/Sming
5  * All files of the Sming Core are provided under the LGPL v3 license.
6  *
7  * PSRAM64.h
8  *
9  * @author: October 2020 - mikee47 <mike@sillyhouse.net>
10  *
11 */
12 
13 #pragma once
14 
15 #include "../MemoryDevice.h"
16 
17 namespace HSPI
18 {
19 namespace RAM
20 {
25 class PSRAM64 : public MemoryDevice
26 {
27 public:
28  using MemoryDevice::MemoryDevice;
29 
30  size_t getSize() const override
31  {
32  return 8 * 1024 * 1024;
33  }
34 
35  IoModes getSupportedIoModes() const override
36  {
38  }
39 
43  bool begin(PinSet pinSet, uint8_t chipSelect)
44  {
45  if(!MemoryDevice::begin(pinSet, chipSelect)) {
46  return false;
47  }
48 
51 
52  // Exit QUAD mode
54  Request req;
55  req.setCommand8(0xF5);
56  execute(req);
58 
59  // Issue RESET
60  req.setCommand8(0x66);
61  execute(req);
62  req.setCommand8(0x99);
63  execute(req);
64 
65  readId();
66 
67  return true;
68  }
69 
70  uint8_t readId()
71  {
72  auto savedIoMode = getIoMode();
73  if(!setIoMode(IoMode::SPIHD)) {
74  debug_e("readId() requires SPIHD IO");
75  return 0;
76  }
77 
78  uint8_t buffer[8];
79  Request req;
80  req.setCommand8(0x9F); // Read ID
81  req.setAddress24(0);
82  req.in.set(buffer, sizeof(buffer));
83  execute(req);
84 
85  setIoMode(savedIoMode);
86 
87  debug_hex(ERR, "ID", buffer, sizeof(buffer));
88 
89  return buffer[0];
90  }
91 
92  bool setIoMode(IoMode mode) override
93  {
94  auto oldMode = MemoryDevice::getIoMode();
95  if(oldMode == mode) {
96  return true;
97  }
98 
99  if(!isSupported(mode)) {
100  debug_e("setIoMode(): Mode %u invalid", unsigned(mode));
101  return false;
102  }
103 
104  Request req;
105  if(oldMode == IoMode::SQI) {
106  req.setCommand8(0xF5); // Exit Quad Mode
107  execute(req);
108  } else if(mode == IoMode::SQI) {
109  req.setCommand8(0x35); // Enter Quad Mode
110  execute(req);
111  }
112 
113  return MemoryDevice::setIoMode(mode);
114  }
115 
116  void prepareWrite(HSPI::Request& req, uint32_t address) override
117  {
118  bool quad = (getIoMode() != IoMode::SPIHD);
119  req.prepare();
120  req.setCommand8(quad ? 0x38 : 0x02);
121  req.setAddress24(address);
122  req.dummyLen = 0;
123  }
124 
125  void prepareRead(HSPI::Request& req, uint32_t address) override
126  {
127  bool quad = (getIoMode() != IoMode::SPIHD);
128  req.prepare();
129  req.setCommand8(quad ? 0xEB : 0x0B);
130  req.setAddress24(address);
131  req.dummyLen = quad ? 6 : 8;
132  }
133 
134 private:
135  HSPI::Request req1;
136  HSPI::Request req2;
137 };
138 
139 } // namespace RAM
140 } // namespace HSPI
PinSet
How SPI hardware pins are connected.
Definition: Common.h:95
void setAddress24(uint32_t address)
Set 24-bit address.
Definition: HardwareSPI/src/include/HSPI/Request.h:133
One bit per clock, MISO stage follows MOSI (half-duplex)
bool begin(PinSet pinSet, uint8_t chipSelect)
Configure the RAM into a known operating mode.
Definition: PSRAM64.h:43
void prepareWrite(HSPI::Request &req, uint32_t address) override
Definition: PSRAM64.h:116
Defines an SPI Request Packet.
Definition: HardwareSPI/src/include/HSPI/Request.h:45
size_t getSize() const override
Definition: PSRAM64.h:30
Definition: Common.h:24
void setClockMode(ClockMode mode)
Definition: Libraries/HardwareSPI/src/include/HSPI/Device.h:108
bool setIoMode(IoMode mode) override
Definition: PSRAM64.h:92
Data in
Incoming data.
Definition: HardwareSPI/src/include/HSPI/Request.h:58
IoMode getIoMode() const
Definition: Libraries/HardwareSPI/src/include/HSPI/Device.h:137
void setCommand8(uint8_t command)
Set 8-bit command.
Definition: HardwareSPI/src/include/HSPI/Request.h:98
#define MSBFIRST
Definition: WConstants.h:62
#define debug_e(fmt,...)
Definition: debug_progmem.h:77
void prepare()
MUST call this first before attempting to re-use a request.
Definition: HardwareSPI/src/include/HSPI/Request.h:70
BitSet< uint8_t, IoMode > IoModes
Definition: Common.h:50
Manage a set of bit values using enumeration.
Definition: BitSet.h:43
#define debug_hex(_level, _tag, _data, _len,...)
Definition: debug_progmem.h:87
void set(const void *data, uint16_t count)
Set to reference external data block.
Definition: Data.h:66
void setBitOrder(BitOrder bitOrder)
Definition: Libraries/HardwareSPI/src/include/HSPI/Device.h:95
Four bits per clock for Address and Data, 1-bit for Command.
uint8_t readId()
Definition: PSRAM64.h:70
#define ERR
Definition: debug_progmem.h:41
bool isSupported(IoMode mode) const
Definition: Libraries/HardwareSPI/src/include/HSPI/Device.h:123
CPOL: 0 CPHA: 0.
void prepareRead(HSPI::Request &req, uint32_t address) override
Definition: PSRAM64.h:125
IoMode
Mode of data transfer.
Definition: Common.h:39
IoModes getSupportedIoModes() const override
Definition: PSRAM64.h:35
PSRAM64(H) pseudo-SRAM.
Definition: PSRAM64.h:25
uint8_t dummyLen
Dummy read bits between address and read data, 0 - 255.
Definition: HardwareSPI/src/include/HSPI/Request.h:56
virtual bool setIoMode(IoMode mode)
Definition: Libraries/HardwareSPI/src/include/HSPI/Device.h:128
void execute(Request &request)
Definition: Libraries/HardwareSPI/src/include/HSPI/Device.h:161
bool begin(PinSet pinSet, uint8_t chipSelect)
Definition: Libraries/HardwareSPI/src/include/HSPI/Device.h:49
Four bits per clock for Command, Address and Data.
Base class for read/write addressable devices.
Definition: MemoryDevice.h:23